1. Field of the Invention
The present invention relates to a semiconductor device fabricating method, and in particular to a semiconductor device fabricating method where semiconductor chips having a plurally lamentable configuration are plurally laminated.
2. Description of the Related Art
A semiconductor chip laminate package is known where plural semiconductor chips are laminated with the purpose of multifunctionalizing a semiconductor device.
As one example of such a semiconductor chip laminate package, there is a stacked multichip package. A stacked multichip package has a configuration where plural semiconductor chips are superposed and mounted on a substrate.
Among methods of fabricating such a multichip package, a semiconductor device fabricating method is known which comprises the steps of: forming first electrode lead-out pads on chip regions of a first semiconductor wafer and forming first conductive posts exposed from the front surface of the first semiconductor wafer on the first electrode lead-out pads to form a first semiconductor wafer, forming second electrode lead-out pads on chips regions of a second semiconductor wafer, forming second conductive posts exposed from the front surface of the second semiconductor wafer on the second electrode lead-out pads, and forming, in the back surface of the second semiconductor wafer, holes in positions facing the second conductive posts by etching or lasering to form a second semiconductor wafer whose second electrode lead-out pads are exposed; and disposing the second semiconductor wafer face-up on the first semiconductor wafer, inserting the first conductive posts into the holes, and connecting the first conductive posts to the second electrode lead-out pads (e.g., see Japanese Patent Application Publication (JP-A) No. 2004-296812).
According to conventionally known fabricating methods such as the semiconductor device fabricating method of JP-A No. 2004-296812, there is the potential for warpage to occur in the semiconductor chips or for the semiconductor chips themselves to break when, for example, the semiconductor chips are laminated. As a result, there is the potential for defects (open defects) in the electrical connections between the semiconductor chips resulting from warpage and breakage of the semiconductor chips to occur.